The subject matter disclosed herein relates generally to electronic digitizers. More particularly, the subject matter disclosed herein relates to analog to digital converters (ADCs).
In many applications, such as diagnostic medical imaging, there is a need to simultaneously or concurrently convert multiple analog signals into respective digital values. For example, diagnostic medical imaging systems such as Computed Tomography (CT) systems, Digital X-Ray systems, Single Photon Emission Computed Tomography (SPECT) systems, and the like use digitization during image acquisition and/or reconstruction. Some of these medical imaging systems use 8 to 14 bit high speed multi-channel ADCs for digitization of acquired data.
Most conventional ADC's use a low noise, high precision comparator and a digital to analog converter (DAC), per channel. The DAC provides a ramp voltage that operates as a reference for sampled and held signals. The speed of an ADC is limited by the rate at which the ramp increases from a minimum signal to a maximum signal, ramp settling characteristics, and power usage for ramp buffers. Accordingly, the speed of the ADC limits the processing speed of the overall system, which can affect the overall performance of the system. Alternate ADC architectures have been proposed to overcome processing speed limitations. One such architecture involves using a DAC per channel along with a successive approximation register (SAR) algorithm. However, the use of the DAC per channel increases the size and power consumption of the ADC.